1. Field of the Invention
The present invention relates to detecting and/or recovering from a timing error for an integrated device, wherein the timing error may result from a variety of conditions, such as, manufacturing or environmental variations, integrated device variations, circuit design issues, device aging, etc.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device or a system on a chip (SoC). Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as any manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
However, as the complexity of the ICs and SoCs increase, so does the cost and complexity of verifying and electrically testing the individual IC or multiple ICs in a system for a SoC. Testing, manufacturing costs and design complexity increase dramatically because of the increasing number of functional pins on the integrated devices and SoC. With the increased number of I/O pins on each integrated device or system, the complexity and cost of testing each integrated device and I/O pin has increased.
Verifying the functionality of an IC is typically accomplished by placing the IC on a tester that includes a tester channel for each I/O pin on the IC. Subsequently, each I/O buffer coupled to an I/O pin is tested for functionality, timing, performance, etc. However, there are often problems associated with testing an IC in this manner. One problem is that testing each I/O pin on an IC is time consuming and often expensive due to test equipment costs. Another problem is that the speed of the test equipment is typically not fast enough to keep pace with the IC. Moreover, existing test equipment is not capable of testing high-speed source synchronous systems. Another problem with testing is the ability to detect timing errors because of the need to make the timing error externally visible to the testing environment.
One example of a circuit schematic for detecting internal timing errors is depicted in FIG. 1. However, this schematic is inefficient in terms of die size and design since it requires a pair of state elements for each signal.